The present invention relates to a scan flip-flop circuit used when a scan test of a semiconductor integrated circuit is conducted, a test circuit using the scan flip-flop circuit, and a method of controlling the test circuit, and specifically, to a technique using a scan flip-flop circuit including two latch circuits of a master latch and a slave latch.
A scan test using an LSSD (Level Sensitive Scan Design) latch has already been known. A technique related to the scan test using the LSSD latch is disclosed in multiple literatures, including for example, “LSSD (Level Sensitive Scan Design)” [searched on Feb. 20, 2011] the Internet <http://www.cedcc.psu.edu/ee497i/rassp—43/s1d089.htm>, “Chapter Design For Testability” [searched on Feb. 20, 2011] the Internet <http://faculty.ksu.edu.sa/musaed/CEN491Doc/Scan-Path.ppt>, and FIG. 6 of Japanese Unexamined Patent Application Publication No. 2005-308421.
FIG. 18 is a view showing a representative LSSD latch circuit disclosed in these cited literatures. As shown in FIG. 18, an LSSD circuit 800 includes a latch circuit 302 which is a Low level latch, and a latch circuit 303 which is a Low level latch.
The latch circuit 302 receives a data input D, a clock signal C, a scan shift data input I, and a scan clock signal A, and outputs data to a data output L1. The latch circuit 303 receives output data from the latch circuit 302 and a scan clock signal B, and outputs data to a data output L2.
The Low level latch (low-level latch) here means a circuit that captures data in a Low level of the clock signal and holds the data in a High level, and the High level latch (high-level latch) means a circuit that captures data in a High level of the clock signal and holds the data in a Low level.
In recent years, semiconductor integrated circuits such as an LSI (Large Scale Integration) include flip-flops (F/Fs) in accordance with a high-speed operation and an increase in size from the point of easiness of timing design. Typically, the F/F is formed of two stages of latch circuits of a master latch and a slave latch. Accordingly, in order to form an F/F of LSSD type using the LSSD latch shown in FIG. 18, a master latch is added to the input side of the LSSD latch.
Hereinafter, a related scan test using the F/F of LSSD type will be described in detail. In the specification, the term “normal operation” means a user circuit operation, the term “capture operation” means an operation to capture test data in a scan flip using a user circuit, and the term “scan shift operation” means the shift operation of test data from one flip-flop to the next flip-flop in the scan test operation.
FIG. 19 is a circuit view showing a Pos-type scan flip-flop circuit (hereinafter referred to as a Pos-type F/F), which is a related LSSD type. The Pos-type F/F here means an F/F that operates in synchronization with the rising edge of the clock signal.
As shown in FIG. 19, a Pos-type F/F 300 includes a latch circuit 301 which is a Low level latch, a latch circuit 302 which is a High level latch, and a latch circuit 303 which is a High level latch.
The latch circuit 301 receives a data input signal D by a data input and a normal clock signal C by a latch signal, and outputs a data signal Y. The latch circuit 302 receives a scan shift dedicated clock signal (scan shift clock signal) SA and the normal clock signal C by a latch signal, and receives a scan shift data input SI and the data signal Y which is the output from the latch circuit 301 by a data input. The latch circuit 303 receives a scan shift clock signal SB by a latch signal and a data output Q which is the output from the latch circuit 302 by a data input, and outputs a scan out signal SO.
FIG. 20 is a circuit view showing an example of detail of the latch circuit 302 of the Pos-type F/F 300 shown in FIG. 19. As shown in FIG. 20, the latch circuit 302 includes a latch circuit 310 which is a High level latch, a selector circuit 311, and an OR circuit 312.
The selector circuit 311 receives the scan shift data input SI and the data signal Y. The selector circuit 311 outputs the scan shift data input SI when the scan shift clock signal SA is in a High level, and outputs the data signal Y when the SA is in a Low level. The OR circuit 312 receives the scan shift clock signal SA and the normal clock signal C, and outputs the resulting signal to a latch signal of the latch circuit 310. The latch circuit 310 receives the output from the selector circuit 311 by a data input and receives the output from the OR circuit 312 by the latch signal, and outputs a data output Q.
FIG. 21 is a timing chart showing an operation of a transition delay test using the Pos-type F/F 300 shown in FIG. 19. FIG. 21 shows operations of the normal clock signal C, the scan shift clock signals SA and SB, the data input signal D, the scan shift data input SI, the output data signal Y of the latch circuit 301, the output data Q of the latch circuit 302, and the output scan out SO of the latch circuit 303. Further, a scan shift cycle SS1 indicates the last three cycle periods of the scan shift operation, a scan capture cycle SC indicates the scan capture operation period, and a scan shift cycle SS2 indicates the first scan shift operation period after the scan capture operation.
First, the scan shift operation will be described using clock cycles C1 and C2. In a period of the scan shift cycle SS1, the normal clock signal C becomes Low level. At time T100, since the scan shift clock signal SA is raised, the latch circuit 302 is in a through state and captures test data D1 from the scan in terminal SI, and outputs the test data D1 to the output data terminal Q. At time T101, since the scan shift clock signal SA is fallen, the latch circuit 302 holds the test data D1 from the scan in terminal SI.
At time T102, since the scan shift clock signal SB is raised, the latch circuit 303 is in the through state and captures the test data D1 from the output data terminal Q, and outputs the test data D1 to the scan out terminal SO. At time T103, since the scan shift clock signal SB is fallen, the latch circuit 303 holds the test data D1 from the output data terminal Q.
Next, the capture operation will be described using clock cycles C4 and C5. At time T110, since the normal clock signal C is raised, the latch circuit 301 holds capture data capA (also shown as cA or A in the drawings) from the data input terminal D and outputs the capture data capA to the data signal Y. Further, at time T110, the latch circuit 302 captures capA which is the output signal data signal Y from the latch circuit 301.
At time T111, since the normal clock signal C is fallen, the latch circuit 301 captures the capture data capB from the data input terminal D. Further, at time T111, the latch circuit 302 holds capA which is the output signal data Y from the latch circuit 301.
At time T112, since the normal clock signal C is raised, the latch circuit 301 holds capture data capB (also shown as cB or B in the drawings) from the data input terminal D. Further, at time T112, the latch circuit 302 captures capB which is the output signal data signal Y from the latch circuit 301.
At time T113, since the normal clock signal C is fallen, the latch circuit 302 holds capB which is the output signal data signal Y from the latch circuit 301.
FIG. 22 is a circuit view showing a Neg-type scan flip-flop circuit (hereinafter referred to as a Neg-type F/F), which is a related LSSD type. The Neg-type F/F here means an F/F that operates in synchronization with a falling edge of the clock signal.
As shown in FIG. 22, a Neg-type F/F 400 includes a latch circuit 401 which is a High level latch, a latch circuit 402 which is a Low level latch, and a latch circuit 403 which is a Low level latch.
The latch circuit 401 receives a data input signal D by a data input, and receives a normal clock signal CB by a latch signal. The latch circuit 402 receives a scan shift clock signal SAB and the normal clock signal CB by a latch signal, and receives a scan shift data input SI and a data signal Y which is the output from the latch circuit 401 by a data input. The latch circuit 403 receives a scan shift clock signal SBB by a latch signal, receives a data output Q which is the output from the latch circuit 402 by a data input, and outputs the signal to a scan out signal SO.
FIG. 23 is a circuit view showing one example of detail of the latch circuit 402 of the Neg-type F/F 400 shown in FIG. 22.
As shown in FIG. 23, the latch circuit 402 includes a latch circuit 410 which is a Low level latch, a selector circuit 411, and an AND circuit 412.
The selector circuit 411 receives the scan shift data input SI and the data signal Y. The selector circuit 411 outputs the scan shift data input SI when the scan shift clock signal SAB is in the Low level, and outputs the data signal Y when the SAB is in the High level. The AND circuit 412 receives the scan shift clock signal SAB and the normal clock signal CB, and outputs the resulting signal to a gate signal of the latch circuit 410. The latch circuit 410 receives the output from the selector circuit 411 by a data input, receives the output from the AND circuit 312 by a gate terminal, and outputs the signal to a data output Q.
FIG. 24 is a timing chart showing an operation of the transition delay test using the Neg-type F/F 400 shown in FIG. 22. FIG. 24 shows operations of the normal clock signal CB, scan shift clock signals SAB and SBB, the data input signal D, the scan shift data input SI, the output data signal Y of the latch circuit 401, the output data Q of the latch circuit 402, and the output scan out SO of the latch circuit 403. Further, a scan shift cycle SS1 indicates the last three cycle periods of the scan shift operation, a scan capture cycle SC indicates the scan capture operation period, and a scan shift cycle SS2 indicates the first scan shift operation period after the scan capture operation.
First, the scan shift operation will be described using the clock cycles C1 and C2. As shown in FIG. 24, at time T200, since the scan shift clock signal SAB is fallen, the latch circuit 402 is in a through state to capture the test data D1 from the scan in terminal SI, and outputs the test data D1 to the output data terminal Q. At time T201, since the scan shift clock signal SAB is raised, the latch circuit 402 holds the test data D1 from the scan in terminal SI.
At time T202, since the scan shift clock signal SBB is fallen, the latch circuit 403 is in the through state to capture the test data D1 from the output data terminal Q, and outputs the test data D1 to the scan out terminal SO.
At time T203, since the scan shift clock signal SBB is raised, the latch circuit 403 holds the test data D1 from the output data terminal Q.
Next, the capture operation will be described using clock cycles C4 and C5. At time T210, since the normal clock signal CB is fallen, the latch circuit 401 holds capture data capA from the data input terminal D, and outputs the capture data capA to the data signal Y. Further, at time T210, the latch circuit 402 captures capA which is the output signal data signal Y from the latch circuit 401.
At time T211, since the normal clock signal CB is raised, the latch circuit 401 captures capture data capB from the data input terminal D. Further, at time T211, the latch circuit 402 holds capA which is the output signal data Y from the latch circuit 401.
At time T212, since the normal clock signal CB is fallen, the latch circuit 401 holds the capture data capB from the data input terminal D. Further, at time T212, the latch circuit 402 captures capB which is the output signal data signal Y from the latch circuit 401.
At time T213, since the normal clock signal CB is raised, the latch circuit 402 holds capB which is the output signal data signal Y from the latch circuit 401.
In the meantime, some circuits including a DDR memory interface or a processor are intended to double throughput without increasing an existing clock frequency. Semiconductor integrated circuits including these circuits have a circuit configuration in which data is transmitted and received at each of the rising edge and the falling edge of clock signals. In short, such a semiconductor integrated circuit includes the Pos-type F/F and the Neg-type F/F connected each other. The problem in the scan F/F using such a typical LSSD latch is that it is impossible to perform a transition delay failure test between the Pos-type F/F and the Neg-type F/F when these F/Fs are connected each other.
Next, a scan test circuit configuration in a circuit in which the Neg-type F/F and the Pos-type F/F are connected will be described. FIG. 25 is a view showing a scan test circuit configuration in a circuit in which the Neg-type F/F and the Pas-type F/F are connected.
As shown in FIG. 25, a scan test circuit 510 includes a Pos-type F/F 300, a Neg-type F/F 400, user combination circuits 1002 and 1003, and a previous scan flip-flop circuit 1010.
The Neg-type F/F 400 receives the output signal from the previous scan flip-flop circuit 1010 by a scan in terminal SI, a scan shift clock signal SA by a scan shift clock terminal SAB, a scan shift clock signal SB by a scan shift clock terminal SBB, the output from the user combination circuit 1003 by a data signal terminal D, and a normal clock signal C by a normal clock terminal CB. A data output terminal Q is input to the user combination circuit 1002.
The Pos-type F/F 300 connects an SO which is the output signal from the Neg-type F/F 400 to a scan shift terminal SI, receives the output from the user combination circuit 1002 by a data input terminal D, the scan shift clock signals SA and SB by scan shift clock terminals SA and SB, respectively, and the normal clock signal C by a normal clock terminal C.
FIG. 26 is a timing chart showing a scan shift operation in a related scan test circuit shown in FIG. 25. FIG. 26 shows changes of signal levels of a Neg-type F/F signal SIG1 and a Pos-type F/F signal SIG2 in the periods of the scan shift cycle SS and the scan capture cycle SC.
As shown in FIG. 26, the Neg-type F/F signal SIG1 indicates signals input to the normal clock terminal CB, the scan shift clock terminals SAB and SBB, the scan in terminal SI and the data input terminal D which are input terminals of Neg-type F/F, and signals output from the data output terminal Q and the scan out terminal SO which are output terminals of Neg-type F/F.
The Pos-type F/F signal SIG2 indicates signals input to the normal clock terminal C, the scan shift clock terminals SA and SB, the scan in terminal SI, and the data input terminal D which are input terminals of Pos-type F/F, and signals output from the data output terminal Q and the scan out terminal SO which are output terminals of Pos-type F/F.
The scan shift cycle SS includes clock cycles C1, C2, and C3. Further, the scan capture cycle SC includes clock cycles C4 and C5.
At time T300, the scan out SO of Neg-type F/F outputs the test data D1 from the scan in SI of Neg-type F/F. Further, at time T300, the Pos-type F/F captures the test data D1 from the Neg-type F/F.
At time T301, the Pos-type F/F outputs the test data D1 from the Neg-type F/F.
As described above, when the transition delay failure test between circuits in which the Neg-type F/F and the Pos-type F/F are connected is executed, the test data D1 from the scan in SI of Neg-type F/F output at time 1300 in one clock cycle period C1 is output from the scan out of Pos-type F/F at time T301, and thus the correct shift operation cannot be performed.
Specifically, it is originally required to supply, to the Neg-type F/F, the scan shift clock signals SAB and SBB shown in FIG. 24 having the opposite polarity from that of the signals shown in FIG. 26, instead of the scan shift clock signals SAB and SBB shown in FIG. 26. However, as shown in FIG. 25, when the Neg-type F/F and the Pos-type F/F are connected, only one kind of scan dedicated clock signals SA, SB or SAB, SBB can be input, which raises the problem that the shift operation is not correctly performed. Accordingly, in the scan test circuit using the related F/F of LSSD type, an inverter for inverting scan dedicated clock signals are provided when the Neg-type F/F and the Pos-type F/F are connected.
The use of the F/F of related LSSD type eliminates the need to secure the hold time (hold free). However, in recent years, the wiring width and the wiring pitches of the semiconductor integrated circuit including LSI have been decreased due to the high-speed operation and miniaturization of the process. Thus, it is necessary to perform the delay failure test in the actual operating frequency in order to screen wiring which may be disconnected or failure in wiring through incomplete VIA.
The delay failure test in the actual operating frequency is performed by the clock signal CB (or clock signal C) shown in FIG. 26. However, as described above, the clock signal CB of Neg-type F/F needs to have the shape shown in FIG. 24. If the clock signal CB shown in FIG. 26 is input, the circuit does not properly operate. Accordingly, also for the clock signal CB, an inverter needs to be provided to invert the clock signal CB.
However, the delay failure in the actual operating frequency needs to be performed under the actual operation circumstances, and it is impossible to perform the test while keeping the inverter provided since the inverter is not used for the original actual operation. Specifically, when the scan test circuit is formed using the F/F of LSSD type, it is absolutely necessary to provide an inverter to invert the scan dedicated clock signal and the clock signal when the Neg-type F/F and the Pos-type F/F are connected. However, when the inverter is provided, it is impossible to perform the delay test in the actual operating frequency.
In a scan test of a recent semiconductor integrated circuit, a flip-flop of MUXSCAN type has been widely used that operates by the same clock signal in both of the Neg-type F/F and the Pos-type F/F (see FIG. 2 and the like in Japanese Unexamined Patent Application Publication No. 2007-127602). Further, while the F/F of LSSD type normally includes three latches, the F/F of MUXSCAN type can be formed of two latches. Thus, the F/F of MUXSCAN type has an advantage over the F/F of LSSD type in that the gate size can be reduced.
Next, the F/F of MUXSCAN type will be described. FIG. 27 is a circuit view showing an F/F of Pos-type which is an F/F of MUXSCAN type. As shown in FIG. 27, a MUXSCAN 500 includes a master latch 510 which is a Low level latch, a slave latch 511 which is a High level latch, and a selector 520.
The selector 520 receives a data signal and scan shift data. Then, the selector 520 selects a scan shift data input (scan in) SIN when a scan mode control signal SMC is in the High level, and selects the data input signal D in the normal operation when the SMC is in the Low level.
A data input terminal of the master latch 510 is connected to the output of the selector 520, and a latch signal terminal of the master latch 510 receives a clock signal CLK.
A data input terminal of the slave latch 511 is connected to a data output terminal of the master latch 510, and a latch signal terminal of the slave latch 511 receives the clock signal CLK.
FIG. 28 is a circuit view showing an F/F of Neg-type which is an F/F of MUXSCAN type. As shown in FIG. 28, a MUXSCAN 600 includes a master latch 610 which is a High level latch, a slave latch 611 which is a Low level latch, and a selector 620.
The selector 620 receives a data signal and scan shift data. Then, the selector 620 selects the scan shift data input SIN when a scan mode control signal SMC is in the High level, and selects the data input signal D in the normal operation when the SMC is in the Low level.
A data input terminal of the master latch 610 is connected to the output of the selector 620, and a latch signal terminal of the master latch 610 receives a clock signal CLKB.
A data input terminal of the slave latch 611 is connected to a data output terminal of the master latch 610, and a latch signal terminal of the slave latch 611 receives the clock signal CLKB.
Next, an operation of the F/F of MUXSCAN type will be described. FIG. 29 is a timing chart showing an operation of a scan F/F of MUXSCAN type (Pos type). FIG. 29 shows changes in the levels of the clock signal CLK, the scan mode control signal SMC, the data input signal D, the scan shift data input SIN, the input M of the master latch, the input S of the slave latch, and the data output Q in the scan F/F of MUXSCAN type (Pos type) in the periods of a scan shift cycle SS (clock signals C1, C2, and C3) and a scan capture cycle SC (clock signals C4 and C5).
In the scan shift cycle SS, the master latch 510 captures data from the scan shift data input SIN according to a falling of the clock signal CLK, the slave latch 511 captures a data signal according to a falling of the clock signal CLK, and outputs the data signal to the data output Q at the next rising. In the scan capture cycle SC, the data from the data input is captured at the rising timing of the clock signal CLK, and the data is output to the data output Q.
FIG. 30 is a timing chart showing an operation of a scan F/F of MUXSCAN type (Neg type). FIG. 30 shows changes in the levels of the clock signal CLK, the scan mode control signal SMC, the data input signal D, the scan shift data input SIN, the input M of the master latch, the input S of the slave latch, and the data output Q in the scan F/F of MUXSCAN type (Neg type) in the periods of a scan shift cycle SS (clock signals C1, C2, and C3) and a scan capture cycle SC (clock signals C4 and C5).
In the scan shift cycle SS, the master latch 610 captures data from the scan shift data input SIN according to a falling of the clock signal CLK, the slave latch 611 captures a data signal according to a rising of the clock signal CLK, and outputs the data signal to the data output Q at the next rising. In the scan capture cycle SC, the data from the data input is captured according to a falling of the clock signal CLK, and the data is output to the data output Q.
FIG. 31 is a view showing a circuit configuration in which F/Fs of MUXSCAN type (Pos type) are connected. The data from the previous scan flip-flop circuit 1010 is connected to a scan shift data input terminal SIN of a MUXSCAN 500a in the left side of FIG. 31, and data output Q is connected to a scan shift data input terminal SIN of a subsequent MUXSCAN 500b. The output from the combination circuit 1000 is connected to the data input terminal.
FIG. 32 is a timing chart showing an operation of the F/Fs of MUXSCAN type (Pos type) shown in FIG. 31. The MUXSCAN 500a and the MUXSCAN 500b receive the same clock signal. Since the data output terminal Q of the MUXSCAN 500a is directly connected to the scan shift data input terminal SIN of the MUXSCAN 500b, the delay is substantially 0. Since the timing for capturing data by the slave latch 511 in the MUXSCAN 500a and the timing for holding data by the master latch 510 in the MUXSCAN 500b are in the same edge, this causes occurrence of hold violations and leaking of data. Accordingly, it is required to provide a delay element for securing the hold time in a scan shift data line between the F/F of MUXSCAN type (Pos type) and the F/F of MUXSCAN type (Pos type).
FIG. 33 is a view showing one example of forming a scan chain by F/Fs of MUXSCAN type. When the Pos-type F/F and the Neg-type F/F are mixed, the Pos-type F/Fs 500 and the Neg-type F/Fs 600 are connected. Accordingly, as shown in FIG. 33, a delay element 1 is required between each of the Pos-type F/Fs 500 and the Neg-type F/Fs 600.
As described above, in recent years, flip-flops of MUXSCAN type have been widely employed as a technique for performing a scan test in the semiconductor integrated circuit in order to perform the delay failure test in the actual operating frequency. However, the shift line of the scan is connected in the shift register structure, and the input clock signal of the previous flip-flop and the input clock signal of the subsequent flip-flop are the same in the shift register structure. Thus, hold time is not sufficiently secured. This causes insufficiency of hold time due to manufacturing variations or clock skew at the time of design. Accordingly, as shown in FIG. 33, it is required to provide the delay elements to secure the hold time.
In summary, since the delay element (buffer) to secure the hold time is required to be provided in all areas between flip-flops operating in the same edge in MUXSCAN, the process to arrange buffers for performing hold compensation is required in a later process. Further, since the buffers are arranged in the later process, it is impossible to provide buffers in target positions when there is no vacant space, which causes deterioration of wiring. Accordingly, the use of the F/F of MUXSCAN type may cause an increase in TAT (Turn Around Time) in the layout process, deterioration of wiring, and an increase in the gate size. In particular, the LSI has recently been increasing in size, which causes a great increase in the gate size and deterioration of wiring.